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Can you define 2 modules on the same page while coding in Modelsim?

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sriramsv

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hi,

is it possible to define 2 modules in the same page while coding in Modelsim.
 

echo47

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question in Verilog

Do you mean "in the same file"?
Yes. That works with any Verilog compiler.
 

always@smart

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Re: question in Verilog

sriramsv said:
hi,

is it possible to define 2 modules in the same page while coding in Modelsim.

yes you may use two module in same file/page, for example :


module abc(a,b,c); //design module
...
...
...
endmodule


module tb_abc; //testbench
...
...
...
endmodule


hope this help

regards,
smart
 

pinu

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question in Verilog

yes,possible,in top-down modelling or bottom up modelling.If u want details I can send it.
 

nanako

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question in Verilog

yes it is possible like

module abc (.....);


endmodule

module def (....);

endmodule

module xyz (....);

endmodule

however when you compile for running you have to invoked the option -v file.v if not some of the modules might not be detected during compile for simulation.
 

sriramsv

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Re: question in Verilog

hi pinu,

yeah i want those details. if u could send me that will be gr8
 

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