Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can we use CSL and FSCL logic as the interface buffer?

Status
Not open for further replies.

chang830

Full Member level 5
Joined
Feb 11, 2006
Messages
267
Helped
14
Reputation
28
Reaction score
3
Trophy points
1,298
Activity points
3,424
Hi,
we know, to reduce the di/dt noise in the mixed signal IC, the CSL and FSCL logic attract moe and more attention. According the information i got by now, it seems that these two logic is only suitable as the internal logic cell. It seems not suitble as the interface buffer which need to dravie the large load.

Would anyone pls. share some information with me? Is it correct for my understanding?

Thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top