cafukarfoo
Full Member level 3
Hi Sir/Madam,
Can we put delay value in the RTL that we want to put inside FPGA for testing?
Is the FPGA synthesis going to honors this delay value?
Thanks in advance for your help.
always @(posedge clk)
val_d <= #1 va;
Can we put delay value in the RTL that we want to put inside FPGA for testing?
Is the FPGA synthesis going to honors this delay value?
Thanks in advance for your help.
always @(posedge clk)
val_d <= #1 va;