capacitance between two pcb traces
Dear FVM, House-Cat,
You guys are very knowledgeable and super helpful in this matter. Thank you very much.
I see the point from FVM and House_Cat description. The redesign of the board should consider this factor:
1. Wider trace up to 0.4mm or more
2. Wider clearance between trace with no gnd line in between.
3. Gnd plane in the 3rd layer is okey to avoid flux.
4. If possible add instrument settling time, in trade of test time increment. (should ask test developer for this one)
5. if possible, higher copper density for high current force lines. (Maybe using beryllium copper??)
I should discuss this with the vendor (Prisma), see if this suggestion is possible.
Honest, you guys rock...thanks for the info, please add more if you think I mistaken for something.
We should have a new sub category in this forum... semiconductor testing and manufacturing.
just a suggestion