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Can two traces create parasitic capacitive effect?

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trace capacitance

For an exact calculation of PCB capacitances, the complete geometry including possible ground planes have to be known. Personally, I wouldn't regard thema as parasitic, rather a natural property of a circuit.

A current (or more exactly the di/dt) mainly causes inductive coupling, no capacitive without a voltage change. Did you really mean 200 A? It would cause about 65 W losses per mm respectively near to 1K/us temperature rise for a 1 oz trace of 0.3 mm width.

capacitance between traces

Crosstalk between two parallel traces from the capacitive coupling is called "Forward" crosstalk. Its magnitude depends on the distance over which the two traces are parallel, the spacing between the traces, the presence of a common plane on adjacent layers, the dielectric constant of the material between the two traces, and the nature of the signal.

In general, the "Backward" crosstalk resulting from the inductive coupling is a far greater problem than the "Forward" capacitive coupling, and tends to overcome the effects of "Forward" crosstalk. Its magnitude depends almost entirely on the distance between the two traces, the distance over which the two traces are parallel, and the nature of the signal.

As you can see, the answer to your question is not quite as simple as it seems on the surface. You need to provide a lot more detail about the signal(s) and the board structure before any meaningful answer can be calculated.

circuit board trace capacitance

Thanks a lot for the answer.
I'm willing to design a board (DIB) for ATE interface. The device to be tested is a high current solid state relay. From the old board, I saw so many test fail marginally but actually its invalid.

When I notice there are one high current line close to GND line (0.2mm apart), the length is about 50mm then they split again. actually the line carry about 50A (200A split to 4 lines).

I'm about to do redesign to this board, that's why I need the advice.

Rikie Rizza

typical trace capacitance

If you are testing a low speed relay I think that the track capacity has not influence.
But if you are in the high speed field (fast switching) maybe is better to check the capacitive amount, you can easily check this with a capacitance meter (also a portable one).

Added after 29 minutes:

I've just found this nice link posted in edaboard by Gundam001. Maybe can be interesting for this topic.
capacitance pcb traces fringing field

Hi Rikie Rizza --

With a 50A switched signal, you are absolutely getting inductive coupling between the two lines during any switching operation. The question is - where is that ground line going, how long is the settle time before test readings are done, and do you have a ground plane in the board to carry the heavy return current? Is the nearby ground line the return line for the high current line next to it?

Capacitive coupling should be of no concern, but inductive coupling at the currents you are using for test is definitely worth worrying about. Look carefully at all layers on the test board, and try to get all other signals on all layers away from those high current lines.
pcb adjacent trace capacitance

Dear Wolf69,

Thanks for the link, very informative.

Dear HouseCat,

The ground line goes from the tester to...device ground pin. Maybe inductive coupling is the real deal, because the invalid test result is the demagnetize test...which means that the device fail to carry conductive loads.

Do you have any suggestion on how to split the lines in a safe way? Should force and sense be close together or not?

Thanks so much for the answer. You guys are helpful.

capacitance of a trace

I would need to know more about how the test is written to give you a good answer. The sense line can run close to the force line for slow speed tests where the load is allowed to stabilze between data readings. If this is a production test where they are trying to crank though as many tests per minute as they can, it would be best to move the sense line away from the inductive field of the force line so the tester can stabilize quickly.

For high current testing, you want the data/measurement lines as far away as possible from the power connections. Additionally, the chip power has to be segregated from the load so you don't feed back switching noise into the control side.

Isn't there an application engineer overseeing the design? You need someone who understands the tester and the test sequence giving guidance on the layout.

parallel track capacitance

Well actually I must give the advice to the design vendor...not myself who build the design. but referring to the old design, I see this problem.

Its a Flex system tester with high power option. Yes this is a production test and each high power test sequence is roundabout 400us...three high power test, 3V (150A max), 6V (200A max) and 12V (100A).

signal trace capacitance

Hi rikie,

A 0.2 mm clearance between a 50A and ground place is not advisable because the current will tend to jump direct to the ground. One more thing how thick and wide is your trace for the 200A? I think you should have more than 200 mils to accommodate that high current.

Its better to increase the clearance, it is better to have 5mm or more..

layout trace capacitance

rikie_rizza said:
Its a Flex system tester with high power option. Yes this is a production test and each high power test sequence is roundabout 400us...three high power test, 3V (150A max), 6V (200A max) and 12V (100A).

I would be concerned about the trace width for the current and test voltages you quote. You say the trace is 0.3mm wide - I assume you're using at least 2oz copper. That means you have a trace resistance of about 0.021 ohms per inch. For your 3V, 150A test, you'll drop about 0.8 volt per inch on each of your four traces. That's too much loss for a reliable test. You need much bigger traces to get the drop under 5-10%, or whatever test spec there is for the device.

If wider traces don't fit for some reason, you may need to consider external bus bars to get the IR drop down to something reasonable.

The other advice still stands. You have large magnetic fields around each of your force lines. You need to keep other signals as far away as possible.

adjacent planes capacitance trace to trace

There have been various comments regarding minimal conductor cross-section respectively trace width for the high current path to control voltage drops and possible temperature rise. The latter depends on the duration of current flow that hasn't been said.

Also most suggestions agree in the point, that you most likely have rather a problem of inductive than capacitive coupling between source and sense circuit. The self and mutual inductances of a given trace geometry can be calculated very exactly with tools as FastHenry. A general approach is to keep the area enclosed by the source and sense loop minimal each and both areas orthogonal regarding inductive coupling.

In addition, planes can act as a shield, that effectively reduce self and mutual inductance. In this regard, it may be advisable to have a low clearance between high current traces and a ground (or other) plane rather than increasing it. The only prerequisition is, that induced eddy currents must not couple into the sense circuit.

parallel tracks capacitance

FvM -

The duration of the current flow has no effect on the IR drop other than the possible temperature rise and accompanying rise in resistance per inch. In this case he has already indicated that the duration is 400us. For the type of test he is doing, the broadband noise generated will probably not be a problem, but losing over one third of his source voltage certainly will - it means the tester needs longer to adjust and settle. He will have additional tester settling problems with inductive coupling between the force and sense lines.

The force and sense lines to which he refers are power supply lines within the tester. Most semiconductor testers use a sense line to keep the supply voltage at the preset value at the DUT itself. Some testers use a four-wire sensing network. The greater the loss at the DUT, the longer you need to let the tester settle before collecting data on the digital lines or analog lines. Production tests are engineered to run as fast as possible while still meeting the validation parameters. His 400us test is probably much too short for the tester to settle. Given that he doesn't have control over the test program, he has to redesign the board to get the DUT voltages closer to the preset values quicker so the tester doesn't have to work as hard.

A copper plane will not shield the magnetic flux produced from a high current trace. The only time a plane can provide any help is if the return path for the current remains on that plane directly under the high current trace. In that event, it is the concentration of the flux within the loop that provides some control - not shielding. That flux is still quite capable of coupling to adjacent signal paths because of the fringing fields. Because of tester resource layout, it's not always possible to get a direct return route across a plane. If you are thinking of Faraday shielding, remember that it has to contain the flux 360deg around the source.

You are obviously a very knowledgable engineer, but test conditions are quite different from steady-state circuit operation. You are trying to verify the operating parameters of a device in the shortest possible time. Normally the progression is from development testing to validation testing, and from there to production test. In production test, speed is the goal because that determines how many devices are sent out the door each day. The development test board is generally "tweaked" to squeeze out as much as possible. It may even be redesigned to add several test sites on the same board so multiple devices can be tested simultaneously. Compromise in optimal layout is often necessary to meet the speed requirements.

capacitance between two pcb traces

Dear FVM, House-Cat,

You guys are very knowledgeable and super helpful in this matter. Thank you very much.

I see the point from FVM and House_Cat description. The redesign of the board should consider this factor:
1. Wider trace up to 0.4mm or more
2. Wider clearance between trace with no gnd line in between.
3. Gnd plane in the 3rd layer is okey to avoid flux.
4. If possible add instrument settling time, in trade of test time increment. (should ask test developer for this one)
5. if possible, higher copper density for high current force lines. (Maybe using beryllium copper??)

I should discuss this with the vendor (Prisma), see if this suggestion is possible.

Honest, you guys rock...thanks for the info, please add more if you think I mistaken for something.

We should have a new sub category in this forum... semiconductor testing and manufacturing. :) just a suggestion :)

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