Can this be done by any mean in verilog

[hallovipin]

input [11:0] adc_data_in;
reg [15:0] sum, check_for_loop;
reg [7:0] j;
reg crossed_sum_threshold;

always @(posedge clk) begin

if(sum>15'b001111111111111) begin
sum=0;
crossed_sum_threshold=~crossed_sum_threshold;
end
else
sum=sum+adc_data_in;
end

always @(crossed_sum_threshold)
for(j=8'd0;j<8'd128;j=j+1) begin
check_for_loop = check_for_loop + sum +j; ///// problem lies here
end



As per SYNTHESIS RULES for loop can only accumulate constants not variable
like:

check_for_loop=check_for_loop+15'd6;

It can not accumulate variables.

What should I do to acheicve this accumulation. Always block can accumulate variable also but always blocks can not be nested (I cant put one always block inside other). One always block has already been used for detecting that sum value has crossed threshold.

Can anybody suggest something

 

[permute]

what do you think your code is doing?

eg, from where i sit, it seems to do:
cfl = cfl*128 + sum*128 + k.

but it does this in a non-ideal manner, and at odd times.

 

[hallovipin]

I have not posted the exact code since its quite big. I had problem with such kind of execution, where a for loop was accumulating a variable. Above code is just a reference for that.

Can u help me finding a solution??

 

[FvM]

It's hard to guess the intended pupose of your code, because you're completely misunderstanding the purpose of the Verilog "for loop" iteration scheme. It's a mean to generate parallel logic, not a sequence in time. A for loop is always "executed" within a single clock cycle.

Typically, a counter which is incremented each clock cycle, is the way to go.

 

[permute]

that still depends, what do you think the above code is doing?

I have an interpretation for what I think the code does. This may be very different than what the code is intended to do.


However, the most likely answer is that HDL is not a programming language. Most likely you have bad expectations on what a for-loop can be used for. Most likely, you want to be able to add N elements in N cycles (accumulating 1 new value per cycle).

as written, the for loop would imply a fairly complex operation that has to complete within 1 cycle.

 

[TrickyDicky]

The best advice when learning HDL:

Draw the circuit first with what you intend to do, then write the HDL of your circuit, never the other way round.

 

[hallovipin]

But my query still remains unanswered.

If not for loop can it be done by any other way.

and it is impossible to draw diagram for complex DSP applications, its easier to write behavioral codes and people are using FPGAs for DSP applications. I think purpose of behavioral is not to make user too worry about circuit.
I may be wrong too..