can the variable hold the value after the control goes out of the process?

[jackg]

Hello!

can the variable hold the value after the control goes out of the process?
For example: I have 2 or more processes in my vhdl code.

1rocess(clk)
begin
if(....condition for the below statements to execute....)
...
...
end process

2rocess(clk)
begin
if(.....condition for the below statements to execute....)
...
...
end process

3rocess(clk)
begin
if(.....condition for the below statements is execute....)
...
...
end process3

First the condition for the execution of process1 is satisfied(assume) and it has a variable say 'a' which has been assigned a value '1'. In the next clk cycle, say process2 is executed. Now, in the next cycle if process1 is executed, will i be able to use the previous 'a' value (=1) now?

regards,
jackg

 

[TrickyDicky]

Your question is irrelavent, because a process never exits. They loop forever, initially running once at the beginning of simulation and re-trigering every time there is an event on any signal in the sensitivity list. So all 3 processes trigger whenever there is a clock edge. So variables never lose their values inside processes because they never go out of scope.

Variables inside functions and procedures go out of scope when teh function or procedure exit, so are lost between function calls.

 

[childs]

As mentioned by TrcikyDicky, process never exits. Your variables are defined outside the process and they are always there for all process to read its value.
But from my experience (been quite a while not touchnig on vhdl), it can only be modified by 1 process throughout your vhdl code. If more than 1 processes in the code try to change the value of the variable, compilation shall fail because there is conflict on the value of the variable. For example, consider the code as below, there might be conflict on the value of variable A when both if statements in process 1 & 2 are true at same time.

1rocess(clk)
begin
if(....condition for the below statements to execute....)
A <= '1';
...
end process

2rocess(clk)
begin
if(....condition for the below statements to execute....)
A <= '0';
...
end process

 

[TrickyDicky]

As mentioned by TrcikyDicky, process never exits. Your variables are defined outside the process and they are always there for all process to read its value.
But from my experience (been quite a while not touchnig on vhdl), it can only be modified by 1 process throughout your vhdl code. If more than 1 processes in the code try to change the value of the variable, compilation shall fail because there is conflict on the value of the variable. For example, consider the code as below, there might be conflict on the value of variable A when both if statements in process 1 & 2 are true at same time.

You are talking about signals. Variables are declared inside processes, functions or procedures. Variables decalred inside a process can only be read and written to inside that process. Signals can be read by any process but writing to them from multiple processes causes issues.

 

[jackg]

Hi all!

So, you mean to say that even the variables will retain their data even though they are not trigger by the clk(say) in every cycle? if the clk is given in the sensitivity list of all the mentioned processess.

regards,
jackg

 

[TrickyDicky]

the processes are triggered, variables are just storage inside a process. The processes will be triggered every single clock cycle, but it may not go through to an assignment path. But yes the variables will hold their value.

 

[jackg]

Thank you very much TrickyDicky!!! This is exactly wat i was searching for.....