Shaber_Mezbah
Newbie level 6
Hi all,
I am designing a high speed pipe-lined DAC.
I am using a differential folded cascode OTA with S/W capacitor CMFB(common mode feedback) circuit for each bit cell. the AC-analysis is showing a 60bd gain. but transient analysis is showing some gain error. in this case, gain is droping by more than 20bd.
first i thought that it might be due to clock feed through. but, i tried for all the recovery techniques like dummy switch and well designed transmission gate.
but, i couldn't improve that gain..
:|:?:Can the S/W cap. CMFB circuit reduce the over all gain of the differential OTA at high frequency...??
I am designing a high speed pipe-lined DAC.
I am using a differential folded cascode OTA with S/W capacitor CMFB(common mode feedback) circuit for each bit cell. the AC-analysis is showing a 60bd gain. but transient analysis is showing some gain error. in this case, gain is droping by more than 20bd.
first i thought that it might be due to clock feed through. but, i tried for all the recovery techniques like dummy switch and well designed transmission gate.
but, i couldn't improve that gain..
:|:?:Can the S/W cap. CMFB circuit reduce the over all gain of the differential OTA at high frequency...??