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can some one help me????

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Cucanh

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hi everyone .Im a student from Vietnam. i have a project and have to submit it to my teacher on the 20th of May . Can you guys here help me with this project. I would really appriciate your help^^^
the project is: design and test 4X4 bit unsigned multiplier using right shift add algorithm.
I have difficluties in describing the two registers. Can you help me write it in VHDL code? thanks very much!!!
I have attached the diagram( the first attached word file:72.0kb,the second is mistaken ) bellow..
thanks in advance^^^
 

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kilbil

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Hi,
with whatever little knowledge i have about vhdl i can't tell you the complete code,but i can share my logic.don't know if its write or not.

1 you will require one entity which will be your multipier, it will have no. of input and output ports required.
2 then as you will be using the diagram for coding the architecture will be structural.
3 then internal connections will have to be declared as signals.
4 then in the main code part you will have to write the actual working.
5 library declarations will be at start.

i hope it helps you a bit.
 
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    Cucanh

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Cucanh

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thanks for your 'little' help. i understand your logic,too. However,the problem here is: I dont know how to describe the 8 bit- two registers in VHDL.
with the first 8 bit register: it has three inputs including cout(1 bit), sum(4 bit),and lower (3 bit ), about the second : 1 input (4 bit sum from the above register) and one ouput(it is the product that we need) One signal between the two registers.. the product includes 4 bit sum, 3 bit-lower, and the last bit is 1.but I still dont know how to write it in vhdl . Can someone else work it out for me? I have added one example , you can see it below.
Hope i will receive nice replying from you^^^
a 0 1 0 1
x 0 1 1 1
----------------------
P(0) 0 0 0 0
+x0.a 0 1 0 1
----------------------
2p(1) 0 0 1 0 1
P(1) 0 0 1 0 1
+x1.a 0 1 0 1
----------------------
2p(2) 0 0 1 1 1 1
P(2) 0 0 1 1 1 1
+x2.a 0 1 0 1
----------------------
2p(3) 0 1 0 0 0 1 1
P(3) 0 1 0 0 0 1 1
+x3.a 0 0 0 0
----------------------
P(4) 0 0 1 0 0 0 1 1
P 0 0 1 0 0 0 1 1
 

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