Can one force ModelSim to flag signals with multiple drivers?

Status
Not open for further replies.
M

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
593
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,681
Signals that have multiple drivers (by mistake of course) may look fine in simulation sometimes and become X at other times. When one tries to synthesize the code, it will always be flagged up as such code cannot be synthesized. Anyway, is there a way to force ModelSim to flag such signals when it is compiling the code so we can remove the mistake?
 

The simple answer is: run synthesis before you simulate.
 

use std_ulogic and std_ulogic_vector instead of std_logic and std_logic_vector. These are unresolved types and it is a error to have multiple drivers.
Otherwise a simulation with a good testbench should catch it. And finally, the synth should get it pretty quick.
 
Its just that the synthesis tool from Altera (now Intel) takes so much longer than ModelSim to do its job
 

You probably can write a TCL script based on getting the nets and using the drivers function on them and then whatever counts list size in TCL. I'm fairly sure there is a way to do this, I don't know if it is built into modelsim as an efficient command though.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…