Can ncxlmode used to compile vhdl model or mixed languaged ?

[yoda]

Hi, is ncxlmode able to compile VHDL model?

I use the following command to compile Verilog and vhdl. Verilog passed. but when the tool see .vhd, it doesn't change to ncvhdl. Anything wrong with my setting on command line below?
I have set the VHDL_SUFFIX to (.vhd) in my hdl.var
ncxlmode \
+mixedlang \
+cdslib+cds.lib\
+hdlvar+hdl.var\
time.v \
-f ./verilog_files \
-f ./vhdl_files\
+access+rw \
+notimingcheck \
-l ncxlmode.log

Appreciate all helps provided. Thanks much!