Can multicycle path be pipelined to achieve single cycle throughput in DC?

[kel8157]

I have a chunk of combo logic (synthesizable netlist) where the shortest path is 1 ns and longest path is 7 ns.
My clock is 5 ns but I need single cycle throughput. If I were to pump input every clk and capture 2 cycles later at every cycle, the shortest path will
have a problem, and longest path may have problem in best corner.
Is DC able to take care of the shortest path here?

 

[asic_service]

To my understanding, DC can't insert DFF for pipeline purpose. This will also causing LEC problem.
I think you have to insert DFF to do the pipeline by yourself.