khaila said:
sure not.
but in VHDL you may use:
x <= (other => '0');
I think it is smartest that Verilog while there is no need to declire the lenght/width!!
In SystemVerilog you have unsized 'b that takes care of this length/width:
x <= 'b0; // No SIZE specification
HTH
Ajeetha, CVC
www.noveldv.com
Added after 2 minutes:
omara007 said:
[
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..
There are array aggregates that let you do this nicely in VHDL. Take a look at VHDL FAQ at
www.vhdl.org/comp.lang.vhdl
I once saw some vhdl code like this :
x = 16#0#
Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!
I've used it, it works fine. IIRC, this was added in VHDL 93, maybe your tool has a flag for V93 and you didn't turn it on?
Regards
Ajeetha, CVC
www.noveldv.com