Can i use GCLK, Vref pin as I/O's in Xilinx Spartan 3A XC3S50A FPGA

[prakashvenugopal]

Hi,


Can i use GCLK and Vref pin as I/O's in spartan 3A XC3S50A? Please let me know.


regards,
V. Prakash

 

[mrflibble]

All the answers you need, just one google hit away

spartan 3 vref as io - Google Search

3rd on the list:

DUAL and VREF pins of FPGA SPartan 3 - Xilinx User Community Forums

So as mentioned in that post, yes you can use VREF as IO. And yes, you can also us GCLK as IO.

And the advice in that xilinx forum post also applies here:
"Read the Spartan 3 datasheet DS099, search for "VREF" and "DUAL". All the information and restrictions are in there."

If you are planning to use the spartan 3 in your project, I highly recommend reading that particular dataheet. It has info on pins like for this question. It has quite a bit of infomation on the block rams, etc.. You can download it here:

http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf