can I use 16-bit Multiplier as 2 seperate 8-bit Multipliers?

[omara007]

multiplier fpga

Hi guys

If I have one 16-bit multiplier, can I use it as 2 separate 8-bit multipliers (probably running in parallel) ? .. is there any multiplication algorithm / multiplier architecture that supports that ?

 

[FvM]

8 bit multiplier

Obviously, you have to cut the carry chain to do so.

Personally, I'm using hardware multiplier of available FPGA devices or vendor supplied arithmetic IP without thinking much about the implementation details, if avoidable.

Recent &#65ltera FPGA (Cyclone II/III) have 18x18 hardware multiplier blocks, that can be used as two individual 9x9 blocks as well.

 

[omara007]

aus 8-bit-multiplizierer 16-bit-multiplizierer

it it the same case if I want to use 1 16-bit ADDERs as 2 8-bit adders .. is there any adder architecture that supports that ? .. if possible, in ASIC, I can chose to implement my adders using this architecture ..

 

[THUNDERRr]

8-bit multiplier

yes, in the attachment u will find the architecture

 

[haneet]

8 bit multiplizierer

i guess you can use the Ripple carry adder architecture for the adder case...

haneet

 

[omara007]

Does any one know if Xilinx supports that ? the same way Altera does support it in its (Cyclone II/III) ??

 

[vipinlal]

Re: can I use 16-bit Multiplier as 2 seperate 8-bit Multipli

I once wrote code for this kind of situation.For increasing the speed I used a bunch of 2*2 or 4*4 multipliers to get the 8*8 multiplier.It is based on the vedic mathematics architecture.The code is given below:

--2 bit multiplication
function mult2( a : std_logic_vector(1 downto 0) ; b : std_logic_vector(1 downto 0) ) return std_logic_vector is

variable a1,b1 : std_logic_vector(1 downto 0):=(others => '0');
variable c1 : std_logic_vector(3 downto 0):=(others => '0');

begin
a1 := a;
b1 := b;
c1(0) := a1(0) and b1(0);
c1(1) := (a1(1) and b1(0)) xor (a1(0) and b1(1));
c1(2) := ((a1(1) and b1(0)) and (a1(0) and b1(1))) xor (a1(1) and b1(1));
c1(3) := ((a1(1) and b1(0)) and (a1(0) and b1(1))) and (a1(1) and b1(1));
return c1;

end mult2;
--4 bit multiplication
function mult4( a : std_logic_vector(3 downto 0) ; b : std_logic_vector(3 downto 0) ) return std_logic_vector is

variable a1,b1 : std_logic_vector(3 downto 0):=(others => '0');
variable c1,c2,c3,c4,c5 : std_logic_vector(7 downto 0):=(others => '0');

begin
a1 := a;
b1 := b;
c2(7 downto 4) := mult2(a1(3 downto 2),b1(3 downto 2));
c3(3 downto 0) := mult2(a1(1 downto 0),b1(1 downto 0));
c4(5 downto 2) := mult2(a1(3 downto 2),b1(1 downto 0));
c5(5 downto 2) := mult2(a1(1 downto 0),b1(3 downto 2));
c1 := c2+c3+c4+c5;
return c1;

end mult4;

Here I am using 2*2 multipliers to get 4*4 multipliers.Same can be done for higher sized registers alsnlu problem is high amount of resource usage.

--vipin
https://vhdlguru.blogspot.com/