Can i force a weak 1 to an internal net in verilog?

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kaushikrvs

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Can i forcce a weak 1 to an internal net in verilog ?

I have a top level , Which has an internal net say VRR . The VRR is usually generated by an analog block , but for some reason , the analog block is still not functional.
I have to force a weak1 to the VRR signal.

I am able to do
force top.VRR = 1;
but when I tried to do;
force (weak1,weak0) top.VRR = 1; it throws an error.
 

Re: Can i forcce a weak 1 to an internal net in verilog ?


weak/strong is a verilog modelling artifice, it is not to be used as a possible value of a signal. signals can be x, z, 1, 0.
 

Re: Can i forcce a weak 1 to an internal net in verilog ?

You need to use a continuous assignment, and then procedurally set the value when you would have done the force.

reg fval = 1'bz;
assign (weak1,weak0) top.VRR = fval;

// in your procedural code
...
fval = 1; // instead of force
...
fval = 1'bz; // instead of release
 

Re: Can i forcce a weak 1 to an internal net in verilog ?

Hello Dave,
Will the above act like a force on a net? because the wire is being driven by some other analog block?
 

Re: Can i forcce a weak 1 to an internal net in verilog ?

A continuous assignment does no override any other stronger assignments. You may need to disconnect the signal manually, or insert a tranif primitive.
 

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