Can I clock gate my block after writing data into it for, says, forever?

[childs72]

Hi, I have some basic idea on how clock gate works & how it may reduce power consumption. Here is a scenario I am curious with:

Says I have a design, and I have a bundle of configuration registers. For operation purpose, I just need to write my configuration registers for once when I power up my IC, and I only read these registers values without modify them later. It seems like I can stop providing clock to the configuration registers after the power up stage, so the config. registers will stay at their values and I can repeatedly use the register values after that. Power saved! Sounds good? :thumbsup:

However, says if I do not turn restart my system for... says, forever! Will the config registers values stay forever while the registers are not being refreshed with clock signal? I am guessing the charges at register output will slowly gone.... Am I correct? If I am, how should I clock gate my config registers?? :thinker:

Anyone may contribute your thought here. Thanks!

 

[ads-ee]

However, says if I do not turn restart my system for... says, forever! Will the config registers values stay forever while the registers are not being refreshed with clock signal? I am guessing the charges at register output will slowly gone.... Am I correct? If I am, how should I clock gate my config registers?

I think you need to go back and study your master slave flip-flop circuit again. That will answer your question.

 

[childs72]

Thanks ads-ee! Took a quick look at flip-flop, so it seems like flip-flop output is merely "refreshed" but not "powered" by clock trigger. I suppose I got myself confused with the idea that DRAM requires periodically "recharge" its content (it's DRAM... right?) :bang: