Can DLL maintain a 50% duty cycle inherently?

[asic_ant]

phase blending dll

Or we have to employ extra module to ensure 50% duty cycle?

 

[ericzhang]

Some delayline aritechiture will make dutycycle
worse, others wont. For the latter one you need
add a duty cycle corrector.

Keep it in your mind that the delay of the corrector
should be the intrinisc delay, which limit your
delayed signal frequency.

 

[rfsystem]

If the delay elements are symmetric or two crosscoupled asymmetric circuits you get complementary signals. These generate 50% duty in a ringoscillator.

 

[pfd001]

symmetric can not ensure 50% duty because of mismatch.

 

[rfsystem]

Hi pdf001,

you clever guy. Also a divide by 2 circuit have mismatches which violate a pure 50% duty cycle requirement.

Or did you have a clever solution to get better than some 10ps accuracy?

 

[zhangseong]

Some delayline aritechiture will make dutycycle
worse, others wont. For the latter one you need
add a duty cycle corrector.

can i know what is this duty cycle corrector comprising of?

and what is the delayline comprising of?

 

[blowfish]

DLL can maintain 50 % duty cycle based upon the circuit used for designing the DLL. Otherwise we need to add a phase blending circuit, which will produce a 50 % duty cycle ....

 

[slchen]

Could you give me some references about phase blending circuit?

Thanks a lot.

 

[DZC]

Here's the paper.