Can anyone tell me how to design a level shift buffer?Thanks

[holddreams]

Can anyone tell me how to design a level shift buffer?

I want to know which parameters are important for the circuit.

Thanks.

 

[hunter694]

Re: Can anyone tell me how to design a level shift buffer?Th

Here is some info:

https://www.daycounter.com/Circuits/OpAmp-Level-Shifter/OpAmp-Level-Shifter.phtml

 

[Vamsi Mocherla]

Re: Can anyone tell me how to design a level shift buffer?Th

Are you talking of a VDD level shifter or level-shift circuit?

One of the good level shifter design is to use a pair of series inverters in Lower VDD Domain. The outputs are driving a differential NMOS transistors with a cross coupled PMOS load. These transistors are in High VDD domain. The outputs can be buffered to enhance the drive strength.

Unfortunately, the opamp solution is limited by speed and settling issues.

I am attaching a rough schematic. Please go through it.

 

[holddreams]

Re: Can anyone tell me how to design a level shift buffer?Th

Yeah,my level shift buffer is just like you draw.
I'd like to know,when you design such buffer,which parameters do you simulate?
Speed,Power consumption?Duty cycle?Or else?

Thanks.

Are you talking of a VDD level shifter or level-shift circuit?

One of the good level shifter design is to use a pair of series inverters in Lower VDD Domain. The outputs are driving a differential NMOS transistors with a cross coupled PMOS load. These transistors are in High VDD domain. The outputs can be buffered to enhance the drive strength.

Unfortunately, the opamp solution is limited by speed and settling issues.

I am attaching a rough schematic. Please go through it.

 

[ynhe]

Re: Can anyone tell me how to design a level shift buffer?Th

1.Driver output rising time/falling time
2.Propagation Delay

 

[Sadegh.j]

Re: Can anyone tell me how to design a level shift buffer?Th

How about a simple common drain, Vgs is the level shifter and it's also a buffer.

 

[mswug]

Actually, you should pay your attention to the balance between rising timing and falling timing

 

[Vamsi Mocherla]

Most importantly, the level shifters should be characterized for speed. Since, the lower voltage inverters need to drive a cap load in the high voltage domain, we need to look into the loading on them. The propagation delay depends on the following factors :

1. Sizing of the second inverter.
2. The latch sizing (PMOS transistors in High VDD domain)
3. Output buffering in the high voltage domain.

--- One small thing, the latch could go in an indeterminate state when the power supply is ramped. Hence it wil leak current in rampup/ shutdown. So, you need also have to come with a figure for this.