naizath12
Junior Member level 1
verilog2001 and conditional generate
i composed the following program.
module division_try(/*divisor,dividend,*/quotient,remainder);
output [3] quotient;
output [3] remainder;
//input [3] divisor;
//input [3] dividend;
reg [3] divisor='b10; //initialise
reg [3] dividend='b1010; //initalise
reg [3] divisor_alias;
initial
divisor_alias=divisor;
reg [3] quotient;
initial
quotient=dividend;
reg aMSB_old;
reg [3] remainder;
reg[7] concat_aq;
integer n;
always
begin
for(n=0;n<4;n=n+1)
begin
concat_aq={remainder,quotient};
concat_aq=concat_aq<<1;
if(aMSB_old)
begin
adder4 ////ERROR HERE////////////////////////
A1(remainder,divisor_alias,'b0,remainder);
end
else if(aMSB_old==0)
begin
sub4 /////ERROR HERE////////////////////////
A2(remainder,divisor_alias,'b0,remainder);
end
aMSB_old=remainder[3];
case (aMSB_old)
1: quotient[0] = 0;
0: quotient[0] = 1;
endcase
end
if(aMSB_old)
begin
adder4 //////ERRORHERE////////////////////////
A3(remainder,divisor,'b0,remainder);
end
end
endmodule
and when i synthesized the code(the modules for adder4 and sub4 which they themselves call another another submodule each)
I wasnt able to synthesize
i got the following error message
ERROR:HDLCompilers:26 - "division.v" line 57 unexpected token: 'adder4'
ERROR:HDLCompilers:26 - "division.v" line 63 unexpected token: 'sub4'
ERROR:HDLCompilers:26 - "division.v" line 77 unexpected token: 'adder4'
have i gone wrong in the flow??.....are v not supposed to use continuous statements inside a procedural block??....(in my case i have tried using assign-deassign & force-releasse also but in vain....
can u ppl help me??...
Added after 4 hours 1 minutes:
ppl the problem is with the flow....
i have instantiated a module within an always statement!!!!!
but i want to call my modules(adder4 and sub4) in a sequential manner....
how do i do this?
thnx in advance
i composed the following program.
module division_try(/*divisor,dividend,*/quotient,remainder);
output [3] quotient;
output [3] remainder;
//input [3] divisor;
//input [3] dividend;
reg [3] divisor='b10; //initialise
reg [3] dividend='b1010; //initalise
reg [3] divisor_alias;
initial
divisor_alias=divisor;
reg [3] quotient;
initial
quotient=dividend;
reg aMSB_old;
reg [3] remainder;
reg[7] concat_aq;
integer n;
always
begin
for(n=0;n<4;n=n+1)
begin
concat_aq={remainder,quotient};
concat_aq=concat_aq<<1;
if(aMSB_old)
begin
adder4 ////ERROR HERE////////////////////////
A1(remainder,divisor_alias,'b0,remainder);
end
else if(aMSB_old==0)
begin
sub4 /////ERROR HERE////////////////////////
A2(remainder,divisor_alias,'b0,remainder);
end
aMSB_old=remainder[3];
case (aMSB_old)
1: quotient[0] = 0;
0: quotient[0] = 1;
endcase
end
if(aMSB_old)
begin
adder4 //////ERRORHERE////////////////////////
A3(remainder,divisor,'b0,remainder);
end
end
endmodule
and when i synthesized the code(the modules for adder4 and sub4 which they themselves call another another submodule each)
I wasnt able to synthesize
i got the following error message
ERROR:HDLCompilers:26 - "division.v" line 57 unexpected token: 'adder4'
ERROR:HDLCompilers:26 - "division.v" line 63 unexpected token: 'sub4'
ERROR:HDLCompilers:26 - "division.v" line 77 unexpected token: 'adder4'
have i gone wrong in the flow??.....are v not supposed to use continuous statements inside a procedural block??....(in my case i have tried using assign-deassign & force-releasse also but in vain....
can u ppl help me??...
Added after 4 hours 1 minutes:
ppl the problem is with the flow....
i have instantiated a module within an always statement!!!!!
but i want to call my modules(adder4 and sub4) in a sequential manner....
how do i do this?
thnx in advance