ok, I found a DFF with Reset signal, I put it here for those who may need it in future
I guess there is no way to build a FF with gate .SUBCKTs, such as NAND gates. I think it only works in theory.
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m0 Q 2 gnd gnd cmosn w=1.75um l=0.5um
m1 2 3 gnd gnd cmosn w=1.75um l=0.5um
m2 4 CLK gnd gnd cmosn w=1.75um l=0.5um
m3 3 R gnd gnd cmosn w=1.75um l=0.5um
m4 5 D gnd gnd cmosn w=1.75um l=0.5um
m5 6 7 gnd gnd cmosn w=1.75um l=0.5um
m6 3 4 6 gnd cmosn w=1.75um l=0.5um
m7 7 CLK 5 gnd cmosn w=1.75um l=0.5um
m8 Q 2 vdd vdd cmosp w=3.25um l=0.5um
m9 2 3 vdd vdd cmosp w=3.25um l=0.5um
m10 4 CLK vdd vdd cmosp w=3.25um l=0.5um
m11 8 D vdd vdd cmosp w=3.25um l=0.5um
m12 3 R 9 vdd cmosp w=3.25um l=0.5um
m13 9 CLK 10 vdd cmosp w=3.25um l=0.5um
m14 10 7 vdd vdd cmosp w=3.25um l=0.5um
m15 7 4 8 vdd cmosp w=3.25um l=0.5um
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