Can anyone help me to solve this FSM design

[santhuz]

Construct a FSM based circuit
for the following specifications:
a.Two 1 bit Inputs: x, y
b. Output: F
c. F is: i:'1' when x and y are unequal for three consecutive clock cycles
ii: else 0

answer must include:a.The state diagram
b.T he associated truth table
c. The simplified boolean expression using Karnaugh maps

 

[ads-ee]

This looks like homework, so I won't give you an answer.

You should start by coming up with a state diagram. Which should look for the 3 or (more?) x != y comparisons. Start with that and post your state diagram when you've come up with up something.

Regards