can anybody tell mehow to decide skew for a chip ?

[harshad]

for first run of backend can anybody tell me how to deside upon insertion
delay and skew.if possible give equations

 

[linuxluo]

hi,
it's depend on your design. but normally according to foundry, they have some rules to follow.

 

[harshad]

Is there any refernece material on this

 

[dada1019]

it's depend on your design and the foundry tech lib, the fundry should give you some rules and advice of it, on the otherhand is important on your experience and designing skill.

 

[eexuke]

it mostly depends on your clock tree.A better clock tree should provide smaller insertion delay and less skew.Anyhow, less skew is of more importance.

 

[wufengbo]

I think you should use timing analysis software to get it .

 

[gentle_man]

timing tree related

 

[sandusty]

Hi, harshad:

I though your question was asking how to set the skew and delay for your first try of the backend clock generation tool. You might be in a dilemma. If you give a tied skew budget, tools will return you a balanced-skew but large-delay tree. If you give a large skew number, your design might fail in the high frequency.

If your clock generated data/control will send into another sync. clock domain, a large delay will cause problem. Please check your application and find if that's the case or not. I met a company design their clock tree with a "very balanced" way in the 2000. They generated 6 ns clock delay!!! Even they pass all simulation, they had a hard time on their system board when the chip came back...

If you are designing a very high frequency system, lousy skew will easily eat up your timing budget!

If you are NOT in the cases stated above. From my experiences, I would like to set the skew budget around 15% of clock period in the first run and then adjust it later.

 

[zyphor]

According to my experience it depends on your design size & technology

for example, for .18 clock skew should be controlled within 0.5 ns to avoid hold time violations .

at first you can set virtual clock uncertainty in synthesis script, then after clock synthesis you should use the real value to replace the virtual one.

 

[xiongdh]

the clock skew that can be accepted for a synchonous one clock digital system.
for positive clock skew.
skew<tdffmin +tpathmin-tdffhold
tdffmin ---- the minimum delay of a DFF register
tpathmin----- the minimum delay of all the path
tdffhold------ the hold time of a DFF register

for negative clock skew
|skew|< Tclock - (tdffmax +tpathmax +tdffsetup)

Tclock ----- the period of the clock
tdffmax----- the maximum delay of a DFF register
tpathmax----- the maximum delay of all the path
tdffsetup----- the setup time of DFF register