These aren't IO types, but layout methodologies. In former times it wasn't allowed to put active layout structures under the bonding pad. Now it is, under certain circumstances - and with special "pad design rules". The 3 abbreviations mentioned above just say what is allowed (or used).
Main pro: more area available for design.
Main con: channel passivation is not properly performed, so you'll have a device performance degradation depending on transistor size and type.