tony_taoyh
Full Member level 2
The procedure :
1) open a empty schematic, insert one instance: analogLib-> vpulse, fill in all the parameters as following:
V3 (net5 net6) vsource type=pulse val0=0.0 val1=1 period=10u delay=1u \
rise=1n fall=1n width=5u
2) Open the ADE, use “Simulation->Netlist->Create”, you will see the above line in the netlist.
3) Go back to the schematic, select the V3 instance and type “q” to get the properties window, change the cell name to vpwl,
and fill in the time0 (for example, 0 ns) and time1 (for example 2ns). Apply the change. Check and save the design.
4) Go back to ADE, use “Simulation->Netlist->Create”, you will see the following line:
V0 (net5 net6) vsource type=pulse delay=1u wave=[ 1n 0.0 2n 1 ]
The correct netlist should be:
V0 (net5 net6) vsource type=pwl wave=[ 1n 0.0 2n 1 ]
Can you see the same problem?
Thanks.
1) open a empty schematic, insert one instance: analogLib-> vpulse, fill in all the parameters as following:
V3 (net5 net6) vsource type=pulse val0=0.0 val1=1 period=10u delay=1u \
rise=1n fall=1n width=5u
2) Open the ADE, use “Simulation->Netlist->Create”, you will see the above line in the netlist.
3) Go back to the schematic, select the V3 instance and type “q” to get the properties window, change the cell name to vpwl,
and fill in the time0 (for example, 0 ns) and time1 (for example 2ns). Apply the change. Check and save the design.
4) Go back to ADE, use “Simulation->Netlist->Create”, you will see the following line:
V0 (net5 net6) vsource type=pulse delay=1u wave=[ 1n 0.0 2n 1 ]
The correct netlist should be:
V0 (net5 net6) vsource type=pwl wave=[ 1n 0.0 2n 1 ]
Can you see the same problem?
Thanks.