Ashen One
Newbie
Hello!
The circuit is a simple one stage amplifier, with a current mirror as the bias tail generator and a diff pair with active load.
Relevant data: Vdd= 1.8V
IMCR+= 1.6V
SR= 5v/us
From the SR I derived that Itail = 50uA.
My purpose is to design the right transistor of the differential couple (connected to output) in order to guarantee that with 1.6V CM in input, everything will still be in saturation, but in order to do this, I should find Beff ("beta eff") and Vth of the NMOS transistor (the one on the right of the diff couple) so to design its aspect ratio W/L
Now, I've tried two different circuits simulation for the sole purpose of learning how to do it:
NOTE: Since my tail current is 50uA for the whole diff pair, this means that in ideal condition my right transistor will drain 25mA, thus I'm using a 25 mA current generator on the drain.
FIRST ONE with diode connection so that the MOS will always work in saturation:
SECOND ONE: with a sweep analysis on DC voltage at the input.
Now to the questions: in either scenario, I know the L is 180nm (channel length), but I do not know W (that is what I'm trying to design). So, how do I do this? Do I just choose a random W and then stick with the result I'm given?
And, once I know this, do I check my result from DC OP, print, click on the MOS?
To be precise: in the lecture I'm following (which is over 15 years old, so that's why I'm here) the man just assumes W= 10um and for some reason changes L to 1um. He uses 50uA for the DC current generator, and then just assumes the printed results from DC OP are right. This ambiguity on the W though makes me doubt the validity of such results.
Thank you.
The circuit is a simple one stage amplifier, with a current mirror as the bias tail generator and a diff pair with active load.
Relevant data: Vdd= 1.8V
IMCR+= 1.6V
SR= 5v/us
From the SR I derived that Itail = 50uA.
My purpose is to design the right transistor of the differential couple (connected to output) in order to guarantee that with 1.6V CM in input, everything will still be in saturation, but in order to do this, I should find Beff ("beta eff") and Vth of the NMOS transistor (the one on the right of the diff couple) so to design its aspect ratio W/L
Now, I've tried two different circuits simulation for the sole purpose of learning how to do it:
NOTE: Since my tail current is 50uA for the whole diff pair, this means that in ideal condition my right transistor will drain 25mA, thus I'm using a 25 mA current generator on the drain.
FIRST ONE with diode connection so that the MOS will always work in saturation:
SECOND ONE: with a sweep analysis on DC voltage at the input.
Now to the questions: in either scenario, I know the L is 180nm (channel length), but I do not know W (that is what I'm trying to design). So, how do I do this? Do I just choose a random W and then stick with the result I'm given?
And, once I know this, do I check my result from DC OP, print, click on the MOS?
To be precise: in the lecture I'm following (which is over 15 years old, so that's why I'm here) the man just assumes W= 10um and for some reason changes L to 1um. He uses 50uA for the DC current generator, and then just assumes the printed results from DC OP are right. This ambiguity on the W though makes me doubt the validity of such results.
Thank you.