Can any one give more details about via

[ksooryakrishna1]

I want some details about design of via and its placement. Could any one have the information or the links.

Thanking you.

 

[leo_o2]

U must check the design rule

 

[forkschgrad]

what exactly do u want?

 

[mvreddy]

Two metal layers connected with Vias ,and ithe size(dimensions)should be Process dependant.

 

[yassin2705]

Via shape depends mainly on the foundary rules because via dimensions are fixed for one each process. For example you may find the contact dimensions are 0.12ux0.12u. Another rule in the minimum allowed layer overlaps which determines the shape of the metal that are connected using this via. For example, you may find M1 overlap contact should be >= 0.1u. Anyhow the design kit you are using should support you with the allowed vias which don't violate the DRC rules.

For the via usage, if you used a big number of vias in parallel, you are decreasing the resistivity of the connection but you are increasing the capacitance, so you should compromize depending on the effect of the connection on your design. You can find the estimated values for the via res. & cap. in the documentation of the process you are using.

I hope this could help.

Thanks!

 

[jecyhale]

I want some details about design of via and its placement. Could any one have the information or the links.

Thanking you.

Design it by the rule, and more vias for reducing the R serise, that's all.

 

[Bin_Wang]

You should place two via as minumal to link the two layers ,because of the manufacture yield.
So you need to modify the LEF for digital PR