can any explain the hold time for me?

[roger]

I got the min path analysis here & I doubt the analysis

Poin Incr path
----------------------------------------------------------------------------------
clock clk(rising edge) 10.00 10.00
clock network delay(propagated) 1.74 11.74
I_TOP_MUL4/I_MUL0/endmask_reg/CK (DFZRBCHD) 0.00 11.74
I_TOP_MUL4/I_MUL0/endmask_reg/Q (DFZRBCHD) 0.26 12.00
I_TOP_MUL4/I_MUL0/endmask_d1_reg/D (DFZRBCHD) 0.00 12.00
data arrival time 12.00

clock clk(rise edge) 10.00 10.00
clock network delay (propagated) 1.74 1.74
I_TOP_MUL4/I_MUL0/endmask_d1_reg/CK(DFZRBCHD) 11.74
library hold time -0.03 11.71
data required time 11.71
----------------------------------------------------------------------------------
slack(met) 12-11.71=0.29

I wonder why hold time should be cut before clk sample edge and use -0.03
rather than +0.03 ?
pls help

 

[silencer3]

it is doing right thing by substracting 0.03. It telling u the slack for hold after the hold time of 0.03 is met.
I doubt that this is really min report.

I just dont know why u r getting clock period of 10.00 in your reports. for min analysis, we just see only the data path delays and clock netwrk delay.

 

[roger]

it is doing right thing by substracting 0.03. It telling u the slack for hold after the hold time of 0.03 is met.
I doubt that this is really min report.

I just dont know why u r getting clock period of 10.00 in your reports. for min analysis, we just see only the data path delays and clock netwrk delay.

Shouldn't setup time be checked before clk sampling edge so use "-"
Shouldn't holdtime be checked after clk edge so use "+" hold time,
Why you said using "-" is correct?

 

[eeeraghu]

u should use setup time delay, but not the hold time delay as it is considered after the clock pulse and we need not bother after the clock pulse of the flip flop.

regards
raghu

 

[roger]

I have checked the library the cell DFZRBCHD
,the hold time did have negative value. What's the meaning of this?

TKS

Added after 55 minutes:

I got it, most of the FF's hold time are negative,
To aoid the clk skew effect.
The data and clk phase in the FF can be adjusted to make the
outside look of hold time became negative.

 

[silencer3]

i think raghu's explanation is wrong. one should consider both setup & hold times. If HOLD fails ur design will totally fail. if setup fails ur design output is wrong. so it is mandatory to consider both.

 

[visualart]

It is the reasson that there are the delay self in the flipflop, This show as a negate value.

 

[amaccormack]

The negtive hold value means that the D can change a very small time after the rising edge of the clock on the clock input to the cell. As said, this means that there is a delay on the clock inside the cell. In technologies below 0.25 micron, there is little point worrying too much about hold times until the final layout is done, becuase wire delays and clock trees can make such a huge difference to min paths.