can a CPLD do this function?

[Mr.Cool]

i am very n00b when it comes to CPLDs so i do not know if it can do this or not.
-can CPLD measure a pulse width, remember how many nanoseconds it was?
repeat this say 10 times and remember the value for each one.
- determine which pulse was the longest
- determine how much shorter each other pulse was with respect to that longest one
- add that difference to each pulse (the longest one gets nothing added to it)

can you give me some key words or even code architecture that can help me narrow down what i need to google search and learn so that i could program such a function?

i have programmed a CPLD many years ago once using simple latter logic. i think for what i want to do above i can not do this with latter logic may need VHDL?

if CPLD can not do this, will an FPGA? i prefer CPLD though for its lower cost and more accurate timing.

 

[srizbf]

finding difference and remembering , adding to each one , can be easily done by any cheapest microntroller.

 

[TrickyDicky]

Modern CPLDs are just small FPGAs. They are programmable so they can do whatever you program it to do. You design the logic.

Measuring a pulse width in single ns will be problematic as it will require a a 1GHz clock. At most, you can get a couple hundred MHz.

 

[KlausST]

Hi,

I'm referring to a Xi line XC9572XL CPLD.

It has 72 macrocells.
If you use a 10 bit counter (needs 10 macrocells )
And you want to safe 10 of those results(each containing 10bits), then you run low on macrocelks.

It makes 100 macrocells in total. Additionally you need extra macrocells for internal logic and outputs.

I'd say even with the next bigger size (144 macrocells) it may be problematic.

Klaus

 

[vGoodtimes]

For argument sake, we should assume delayed versions of the pulse are presented to the device. eg, a 250MHz clock sampling 16 versions of the pulse with 250ps delays.

 

[Mr.Cool]

i think my original description was not accurate. i have a signal coming in on an I/O when this pin transitions high, counter starts. and it continues counting until some other I/O pin transitions high. repeat this 10 times. etc. etc.

20ns resolution is fine for me so i was thinking 100MHz clock would be good.

can you tell me which type of counter to use?
what is the function called when you save the value to a 10-bit register?

what is your feeling for a 1.8V CPLD surviving in a high noise application? i am liking Altera Max V, 192 macrocell. i've used a CPLD in same environment before years ago but it was 5V part. new ones are all 1.8V (and going lower!)

 

[andre_luis]

can you tell me which type of counter to use?
what is the function called when you save the value to a 10-bit register?

Some processes do not have a specific denomination for their functions, don't matter what kind of logic blocs are implemented. You simply describe the entire behaviour in some descriptive language and see what is synthesized.

So, having this as a fact, the next step before starting ( would say, mandatory ) is you sketch a diagram of what you want to do, so that can use this like a checklist to verify if your code is doing everything as expected.

 

[Mr.Cool]

just incase this is important, i picked CPLD instead of say a microcontroller because of the 20ns measuring requirement and high noise environment. i just assume microcontroller can not perform well in that area. seems like the CPLD i need is also cheaper than low cost MCU so that is a small factor but not a big deal as this is not production, just a one-off design at this time.

 

[KlausST]

Hi,

10 bit counter and 20ns resolution means max 20 us measurement time.

10 x 10 bits stored data means 100 mc.
You need a synchronous counter, all input signals synchronized to your master clock.
Rising edge detect needs two mc each input.

Noisy environment:
We use CPLDs next to switched (phase controlled) 6000A lines 2500V 50 Hz AC, 500ns rise time. For sure a good layout and good power supply filtering is urgent. For data transmission we use POV. I never recognized a problem with this environment, neither with CPLD, nor with microcontroller, no shielding case.

Klaus

 

[Mr.Cool]

to get the 20ns resolution, can i use internal CPLD clock divider to get the 20ns clock i want? so, i could use an external 10MHz oscillator and then internal clock divider of 5?

 

[KlausST]

Hi,

10MHz means 100ns.

A clock divider divides frequency.
Divide 10MHz by 5 and get 2MHz.
2 MHz means 500ns.

Klaus

 

[FlapJack]

For data transmission we use POV.

Klaus

What is POV

 

[Mr.Cool]

ah.. so i need external 50MHz oscillator to get clock frequency to give me the 20ns resolution i want (no clock divider)

 

[KlausST]

Hi,

What is POV

I meant POF, plastic optical fiber.

Klaus

 

[TrickyDicky]

ah.. so i need external 50MHz oscillator to get clock frequency to give me the 20ns resolution i want (no clock divider)

Possibly - but if the input signal is asynchronous to the clock, you will need a faster clock as you wont sample the signal at the start of the pulse.

 

[ads-ee]

Mr.Cool, Been watching this thread for the last week and I've come to the conclusion that you are doing a bottom up design and have decided on a part before knowing fully what the part needs to do.

I suggest you step back and do as was suggested in post #7

So, having this as a fact, the next step before starting ( would say, mandatory ) is you sketch a diagram of what you want to do, so that can use this like a checklist to verify if your code is doing everything as expected.

Create a design that does everything you require (ignoring clock frequency input used) including the sample rate required to meet the performance requirements for resolution and accuracy. Keep iterating on the design until you have something that will meet all your requirements. Then pick the component used based on what your design requires, instead of picking a component and then trying to force your design to fit. Only with extensive experience comes the ability to pick a component that should work for an application, even then there is more risk with it being the wrong choice.

I kind of suspect you would be better off using a small FPGA like the Lattice or Microsemi line of FPGAs (instead of macrocell based CPLDs) and using a 200 MHz clock (5 ns resolution) which will also improve the accuracy of the pulse width matching you are trying to accomplish.

 

[Mr.Cool]

agreed about doing the design first and then see what chip you need. i have no limit to space so its OK this approach. i'm just learning a bit about the parts and stuff. for cost reason and also cause i'm totally new, i don't want to do this in an FPGA. the reason i am quickly trying to ball-park determine which CPLD to use is because i am actually trying to draw my schematic now and wanted to pick the part to use rather than pick one as a place holder.

as for sketch, i'm not sure how to sketch this; here's what i want to do:
1. CPLD issues a pulse on I/O_a (where a just means any available I/O i just happen to call "a")
2. CPLD starts a counter at the same time as 1.
3. CPLD counts until pulse received on I/O_w. total time is less than 1us and i would like 20ns resolution so this gives idea on size of counter
4. store count in step 3 in memory
5. repeat ten times steps 1 through 4 but issues a pulse on different I/O's (received on same I/O_w) and store in different memory
6. of the 10 stored count values, which one is the longest? and by how much

i think a synchronous clock is fine because clock starts at same moment CPLD issues first output I/O. although the received pulse on I/O_w is random, at most this will add one extra clock cycle making measurement 20ns inaccurate which is fine. For this reason is why i chose 20ns cause this is my max acceptable measurement error.

now i go read datasheet, make sure 50MHz clock is acceptable

with the above, now i know what the timing of the system connected to I/O_a, I/O_b, I/O_c .. etc.

so this is why Klaus' message about LE's and MC's (i had to look up what these letters meant) was meaningful. so i can get a sense of how much memory i need. without optimizing the code above in any way, i see i need a 6-bit counter. this takes 6 LE's. i can probably re-use the same counter in memory for each run, so here i can make an obvious optimization of the code... only ONE counter needed.
if i store each timer for all 10 runs, that is 6 bits of stored data, is that 6x10 = 60 macrocells?

then i have to do some arithmatic to determine by how much each stored count value is different. i don't have a sense of how much memory this takes but i suspect not much in comparison to how much is available on even the smallest CPLD.

so looks like MC's is my limiting factor. looking at Altera Max 5 (i pick this brand at random) i see maybe 5M160Z is the part suitable to my needs.

 

[FvM]

Comparing 6-bit numbers involves an effort similar to a full adder, doing this sequentially requires a state machine and either a large mux or addressable memory. The logic is unlikely to fit 160 LEs respectively MCs. A larger MAX V should do, I would prefer a small MAX 10 which offers also block RAM.

You can start with sketching a block diagram, write HDL and compile for test to evaluate the resource requirements.

 

[ads-ee]

The Microsemi ProASIC3 Nano is pretty price competitive with CPLDs and tend to have way more FFs available, but significantly less I/O for a given number of "gates". The architecture of the part is somewhat different and the tools are not as nice as Vivado or Quartus but they do work.

The largest part is only ~$20 on digikey about the same as the largest part in a MAX V. The MAX has more I/O 271 vs. 68 and the Nano has more logic ~3K LE equivalent vs. 2210.

I kind of doubt you need such a large part, but that is just an example of how a non-traditional FPGA from other than Altera/Xilinx can be price competitive with CPLD offerings.