I expect, that FPGA Advantage is using hardware specific libraries for entities as FPGA internal RAM, PLLs, I/O-cells. Basically, the documented HDL primitives, provided by ISE or Quartus can be used. FPGA Advantage place and route is performed by vendors tools (e. g. Quartus) anyway.
Regarding complex IP from FPGA vendor or third parties, the situation is more complicated. Most of the cores is distributed as encrypted HDL, in a vendor specific format not usable with other tools. So the IP in question has to be delivered in a FPGA Advantage specific distribution.