nashafi
Member level 1
Hi,
I am using Mentor's Precision RTL in shell mode and trying to run multiple tcl files using one main file
e.g main file
load.tcl
dofile file1.tcl
dofile file2.tcl
and
file1.tcl and file2.tcl are identical and look like this
set_working_dir C:/test/case1
add_input_file {C:/test/case1/acs.vhd C:/test/case1/bmm.vhd C:/test/case1/bmu.vhd C:/test/case1/bmu_top.vhd C:/test/case1/butterfly.vhd C:/test/case1/control_logic.vhd C:/test/case1/data_path.vhd C:/test/case1/declarations.vhd C:/test/case1/kernel.vhd C:/test/case1/kernel_arch.vhd C:/test/case1/kernel_beta.vhd C:/test/case1/kernel_control.vhd C:/test/case1/kernel_top.vhd C:/test/case1/llr.vhd C:/test/case1/llr_top.vhd C:/test/case1/map_decoder.vhd C:/test/case1/memory_bank_bm.vhd C:/test/case1/memory_bank_sm.vhd C:/test/case1/mux.vhd C:/test/case1/mux_bmm.vhd C:/test/case1/mux_bmm_core.vhd C:/test/case1/mux_kernel.vhd C:/test/case1/mux_kernel_beta.vhd C:/test/case1/mux_kernel_smm.vhd C:/test/case1/mux_smm.vhd C:/test/case1/mux_smm_bsmm.vhd C:/test/case1/mux_smm_fsmm.vhd C:/test/case1/reg.vhd C:/test/case1/smm.vhd C:/test/case1/smm_mux_core.vhd C:/test/case1/sram_bm.vhd C:/test/case1/sram_sm.vhd C:/test/case1/up_down_counter.vhd}
setup_design -frequency=40
setup_design -manufacturer Xilinx -family {VIRTEX-II Pro} -part 2VP7fg456 -speed 6
move_input_file -to 0 -from 7
move_input_file -to 1 -from 0
move_input_file -to 32 -from 15
compile
synthesize
place_and_route cl
remove_design -all
setup_design -reset
when it executes every thing . it some how cannot come out of the file1.tcl to go back to file2.tcl through the load.tcl
Any suggestions ? tips ?
Thanks,
Nauman
I am using Mentor's Precision RTL in shell mode and trying to run multiple tcl files using one main file
e.g main file
load.tcl
dofile file1.tcl
dofile file2.tcl
and
file1.tcl and file2.tcl are identical and look like this
set_working_dir C:/test/case1
add_input_file {C:/test/case1/acs.vhd C:/test/case1/bmm.vhd C:/test/case1/bmu.vhd C:/test/case1/bmu_top.vhd C:/test/case1/butterfly.vhd C:/test/case1/control_logic.vhd C:/test/case1/data_path.vhd C:/test/case1/declarations.vhd C:/test/case1/kernel.vhd C:/test/case1/kernel_arch.vhd C:/test/case1/kernel_beta.vhd C:/test/case1/kernel_control.vhd C:/test/case1/kernel_top.vhd C:/test/case1/llr.vhd C:/test/case1/llr_top.vhd C:/test/case1/map_decoder.vhd C:/test/case1/memory_bank_bm.vhd C:/test/case1/memory_bank_sm.vhd C:/test/case1/mux.vhd C:/test/case1/mux_bmm.vhd C:/test/case1/mux_bmm_core.vhd C:/test/case1/mux_kernel.vhd C:/test/case1/mux_kernel_beta.vhd C:/test/case1/mux_kernel_smm.vhd C:/test/case1/mux_smm.vhd C:/test/case1/mux_smm_bsmm.vhd C:/test/case1/mux_smm_fsmm.vhd C:/test/case1/reg.vhd C:/test/case1/smm.vhd C:/test/case1/smm_mux_core.vhd C:/test/case1/sram_bm.vhd C:/test/case1/sram_sm.vhd C:/test/case1/up_down_counter.vhd}
setup_design -frequency=40
setup_design -manufacturer Xilinx -family {VIRTEX-II Pro} -part 2VP7fg456 -speed 6
move_input_file -to 0 -from 7
move_input_file -to 1 -from 0
move_input_file -to 32 -from 15
compile
synthesize
place_and_route cl
remove_design -all
setup_design -reset
when it executes every thing . it some how cannot come out of the file1.tcl to go back to file2.tcl through the load.tcl
Any suggestions ? tips ?
Thanks,
Nauman