calling module in verilog

[Mina Magdy]

Hi
i have a problem in calling module in verilog that when i call a module that make alot of calculation( module calc) it gives me the o/p delayed a clock
and also another module for ram and module for rom thats also delay one clock so when i take the delayed o/p from the (module calc) and but it in the (module RAM) it put the values at wrong places in the ram.

module calc is consists of a module for lookuptable(module LUT) and another module for adding and subtract floating point(module addsub).

i need a form of module that doesn't delay (what could make a delay in a module to avoid) because my system is consists of alot of modules in side each other.

please help me if you can or if you have any suggestion.

 

[TrickyDicky]

The modules probably have a 1 clock cycle delay, as is normal. If you cannot modify the pipeline delay, then register the other signals in parralell

 

[Mina Magdy]

The modules probably have a 1 clock cycle delay, as is normal. If you cannot modify the pipeline delay, then register the other signals in parralell

what do you mean by register the other signals in parralell?

 

[TrickyDicky]

Add extra registers into the pipeline to ensure nothing is delivered at the wrong time.

 

[Mina Magdy]

Add extra registers into the pipeline to ensure nothing is delivered at the wrong time.

you mean add enable to the ram

i made that but still the problem appear as when i enabke it read the old o/p in that clock

 

[TrickyDicky]

no. not an enable

How about you post some code, your testbench code and the waveform, plus explain a bit better what you expect.