Sorry to trouble, but why do we use Gate-level instead of transistor-Level?
I use transistor-Level to do the post-layout simulation, the NF of the LNA degraded too much, what is the problem?
many thanks!!!
yhq0413 said:
Hi all
NOW I use calibre extraction the RC using calibreview,
because RFMOS model
extraction type is Gate-level
I use a xcell file.
Layout source
p18_ckt_rf p18_ckt_rf
n18_ckt_rf n18_ckt_rf
but there are some warnings: HCELL p18_ckt_rf not located or not allowed
HCELL n18_ckt_rf not located or not allowed
the calibre is 2006.01