Looks like you have no substrate or well ties in your layout
hey thanks for the reply. it seems you might be right. I have to at least connect the nwells to metal 1 here and metal 1 gnd to the p sub. I am using tsmc 180 and the layer pallet selection it doesn't appear that I have a via options M1 to NWELL and M1 to sub. Does anyone know if the NWELL pin and PWELL pin will be sufficient in this case?
I can place a piece of an active (diffusion) inside Nwell covered by NPLUS, and piece of active/diffusion in SUB (covered by PPLUS).
Connect these diffusions to M1 by CONTACTs.
These will form (through LVS / extraction) a well tie.
Do you have your pins on the proper layers? Are you DRC clean?
I suspect there are metal_1 dwg (drawing) and metal_1 pin layers.
I have been using metal 1 pin layers. should I have been using the drawing layers instead?
No, the pin layer actually is correct for the pin names.
There must be a different reason for the LVS ports error.
Perhaps the pin layers hadn't been included for the extraction? Can you select the pins in the extracted view?
Yes, that's correct. Same with ASSURA LVS.DIVA only seems to compare the schematic with the extracted view.
I've no experience with Calibre LVS, so I can't help, sorry. But I think extraction is necessary in any case - how would you get a layout netlist (for comparison) by other means? I guess Calibre runs extraction in background anyway.All the examples of Calibre LVS I have seen so far seem to compare the layout (before extraction) with the schematic view.
Try looking in your extract rules and see if they tell specifically which layer spins must be on.
Try different combinations layers for your pins and make sure connectivity is on the pin. Place a text label on metal1_pin. Try it on metal1_drw.
Just some ideas.
Note: also before I forget, you don't need to parasitic extraction for running LVS in calibre. This is unlike cadence's DIVA and Assura (erikl said that ASSURA works the same as DIVA in this regard) Extraction doesn't seem to be separate step and is done by the LVS tool.
Extraction for LVS and a parasitic extraction are two different things. Assura is run directly in Cadence. It may appear that an extraction is not being performed but it actually is. You have an extract rule set that creates a netlist of the layout. You will also have a compare ruleset that compares the extracted netlist vs the schematic netlist.
Calibre works the same but on a stream file and not DFII data.
Rulesets for parasitic extractions are written to extract parasitic devices (Rs, Cs & Ds) from a layout. I believe some tools can back annotate those devices into your schematic netlist.
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