Two possibilities:pokemonstation said:Calibre LVS does not recognize the pins I placed in the layout.
yes.pokemonstation said:Do I have to have a successful and error-free LVS run in order for this to work?
Thank you for your back-info! Perhaps the following note might help?pokemonstation said:Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.
I also disabled the environment variable PEX_RUN = TRUE, which always creates a diode between VDD and ground rail (and forces me to add a diode in my schematic)
Still, with a working LVS, I still cannot get the parasitic extracted netlist to use the net names from either the schematic or the layout. Does anyone know solutions to this?
Hi Usman,Usman Hai said:"Now, within ADE add the netlist to the model setup".
I dont understand this point. Can you please elaborate on this point.
Sorry, no. I've just used the extracted netlist(s) for postLayout simulation.Usman Hai said:Also, do you have experience using calibreview.
See this thread! **broken link removed**ansonyeap said:Can you suggest any more details reference or guides? thank you...
Try here!ansonyeap said:... calibre xRC, parasitic extraction and post-layout simulation.... where can i find the information?
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