Calculation of Setup time and Hold time

[anan_tv]

Haiii,

How to calculate Setup time and Hold time manually???

How does they differ for FPGA and ASIC????

Thank you

 

[semiconductorman]

setup and holdtime will be specified by the library vendor.

 

[anan_tv]

haiii ,

I think the vendor will be giving it for ASIC only.

what abt FPGA???

also for any circuit , how to caluculate them???

 

[anjali]

even for FPGA, there will be tech specific libraries. setup & hold periods r given in those libs.

 

[farhada]

Take a look at:

**broken link removed**

It has a good explanation about how to calcualte the S&H.

Cheers,
/Farhad

 

[anan_tv]

haii ,

I already seen more websites for the formulaes.

also there are lot of variants in the formulaes such as:

Hold time <= Σ shorest contamination path delays
<= propagation delay
<= clk-Q delay + combinational path delay - clk skew

Setup time <= clk period - ( clk-Q delay + combinational path delay + clk skew)


Also w.r.t clock

clk-low >= Setup time

clk-high <= Hold time

which of the above has to be used for checking violations??? & for requirements???


[/list]

 

[beckchm]

in general , different libs have different time constraints.

 

[Yun Lin]

if you want to calculate, the simulation can tell you the setup and hold time.
The setup and hold time is the point that the function is fail.

 

[bansalr]

The setUp and Hold time are defined by the Library vendors.

In FPGA the data sheet provides the setup and hold time.

 

[cfriend]

Calculating the setup and hold times at the pins of a chip
I'm recording this information not because it is difficult to rederive, but because I've derived it at least twice now, and it always takes me about half an hour. Next time I need this information, I'll know where to look it up quickly!

Summary
A positive setup time indicates a time before the active edge of clock, a negative setup time, after.
(setup time at pin of whole chip) =
(setup time of flip-flop data pin)
- (min clock delay from chip pin to FF pin)
+ (max data delay from chip pin to FF pin)

A positive hold time indicates a time after the active edge of clock, a negative hold time, before.

(hold time at pin of whole chip) =
(hold time of flip-flop data pin)
+ (max clock delay from chip pin to FF pin)
- (min data delay from chip pin to FF pin)


Details
Suppose that you have a chip with a data input pin whose signal goes through some delay on chip (e.g., the input pad, RC delay on the wire to a FF (flip-flop) input, some logic inserted expressly for adding delay) before being sampled at a FF. This FF responds to active edges of a clock pin, which is also delayed before it reaches the FF clock input.
Given the setup and hold times of the FF data input relative the the FF clock input, what are the setup and hold times of the pin A relative to the the pin CK of the chip?

Here are some abbreviations used below:


cf - time when active edge occurs on Clock pin of Flip-flop
cc - time when active edge occurs on Clock pin of the whole Chip
df - time of a transition on Data input of Flip-flop
dc - time of a transition on Data input of the whole Chip
Let's specify the setup-hold window of the FF as follows. The FF will reliably sample the data input as its next state as long as the data input of the FF remains stable in the interval [cf-fsetup, cf+fhold], or:

df is not in [cf-fsetup, cf+fhold]
Alternately:


(df < cf - fsetup) (1)
OR
(df > cf + fhold) (2)
then the FF will reliably sample the data input as its next state. Also suppose that the delay from a transition on the data pin of the whole chip to a transition on the data input of the FF is in the range [dmin, dmax]. Stated another way:


(dc+dmin <= df) (3)
AND
(df <= dc+dmax) (4)
Finally, suppose that the delay from an active transition on the clock pin of the whole chip to an active transition on the clock input of the FF is in the range [cmin, cmax].


(cc+cmin <= cf) (5)
AND
(cf <= cc+cmax) (6)
Now, we wish to determine the smallest interval that the data pin of the whole chip must be stable, of the form [cc-csetup, cc+chold], to guarantee that the FF data pin meets its setup and hold times.

I'm going to derive these "backwards", with a sequence of statements of the form:

statement 1
<== { reason 1 }
statement 2
<==> { reason 2 }
statement 3

This means that statement 2 implies that statement 1 is true, with any justification or comments given as reason 1. It also means that statement 2 is true if and only if statement 3 is true, with any justification given as reason 2.

Here we go, for the setup time:

df < cf - fsetup
<== { (4) }
(dc+dmax) < cf - fsetup
<== { (5) }
(dc+dmax) < (cc+cmin) - fsetup
<==> { algebra }
dc < cc - (fsetup - cmin + dmax)

The final result implies that the setup time at the whole chip is (fsetup - cmin + dmax), as summarized at the beginning.

Now for the hold time, which is derived almost identically:

df > cf + fhold
<== { (3) }
(dc+dmin) > cf + fhold
<== { (6) }
(dc+dmin) > (cc+cmax) + fhold
<==> { algebra }
dc > cc + (fhold + cmax - dmin)

The final result implies that the setup time at the whole chip is (fhold + cmax - dmin), as summarized at the beginning.

Added after 35 seconds:

**broken link removed**

 

[Resistance]

Hi,


Set up times and hold times of a flop or latch are specified by the vendor..

but these depend on the technolgy u would be choosing and many more factors..

but set up times for a port(input or output) is different and ought to estimated by the user..

r u interested in that?

Plus for FPGA and ASIC dont have diff concepts for set and hold times..
may be the values may differ .

plus if u are taking about pin set up times then difference does exist..