Calculating dynamic power in synthesis?

Status
Not open for further replies.
B

biju4u90

Full Member level 3
Joined
Dec 10, 2014
Messages
172
Helped
3
Reputation
6
Reaction score
3
Trophy points
18
Activity points
1,437
The ASIC synthesis tools like Cadence RTL Compiler will report static and dynamic power consumed in your design in the power reports. How does the tool calculate the dynamic power even without the switching information??
 

The power consumption due to switching losses occurs maximized somewhere between steady logic levels, because neither the current nor the voltage will be null. How could the tool calculate it without any stimulus along time ?
 

It's most likely an estimate based on the SDC constraints for the clock and a 12.5% toggle rate of all FFs that use that clock. It's therefore likely to be very inaccurate, probably in excess of +/-30% off.

FPGA dynamic power analysis tools for both Altera and Xilinx do exactly this type of calculation and report that the results have very low accuracy.
 
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…