tarjina
Junior Member level 3
I am trying to implement add ALU in verilog.
I have to set the overflow flag from addition.
What I have got from googling is, if the operation is carried on 2's complement,
overflow = c(i) xor c(i-1)
But, my confusion is as follows:
let's say I am adding 16'hFFFF + 16'hFFFF
so, i should get an overflow =1.
but, according to overflow equation, c(14) =1 and c(15) = 1. So overflow would be zero. But then how do I get the overflow.
Thanks in advance.
I have to set the overflow flag from addition.
What I have got from googling is, if the operation is carried on 2's complement,
overflow = c(i) xor c(i-1)
But, my confusion is as follows:
let's say I am adding 16'hFFFF + 16'hFFFF
so, i should get an overflow =1.
but, according to overflow equation, c(14) =1 and c(15) = 1. So overflow would be zero. But then how do I get the overflow.
Thanks in advance.