Yeah, I know that Since Virtuoso is used for digital back end design and analog circuits design. I thought you plan to to mixed (VHDL-Spice) simulation under a cadence+Spectre envirnement. Btw, it would be a normal task If you are familiar with back end. Your task will consist in gathering the digital parts (a netlist generated by design compiler) and the layout out of the analog circuits.
Typically you would import a post-layout Verilog netlist and DEF file. The Verilog netlist is used to create a schematic and the DEF the layout. You can then instantiate this as you would any other cell in your design.