Cadence Virtuoso errors in DRC layout

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Hi, I'm a newbie for cadence virtuoso layout. When I ran the DRC report, I met three errors. I struggled a long time. Error 1 and 2 are the same MOSFET. It's PMOS. It's screenshot 6. Error 3 is screenshot 7. It's NMOS. I also attached the schematic. It's screenshot 9. May I know how to deal with those three errors? Appreciate it a lot.
 

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Check if you have put the substrate taps within 10um distance from the respective source/drain diffusion areas. That is the error you are facing.
 

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