Dr. von Rosenstein
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Hi,
I have a testbench-schematic for an rectifier:
If I start Cadence and open this schematic and ADE GXL with the related adexl view and I run the simulation everything is alright. But if I subsequently "Check and Save" this schematic without any changes in the schematic and after that I klick "Run Simulation" again, then the simulation fails and in the output log I can read:
Warning from spectre in `ideal_balun', during circuit read-in.
WARNING (SFE-618): "input.scs" 190: Unterminated subcircuit. Terminating statement at the end of file.
.
.
.
Error found by spectre during circuit read-in.
ERROR (SFE-3): "input.scs" 190: `ideal_balun' is being redefined. It was defined at `input.scs' 77 before. Remove or rename either of them.
If I close ADE and reopen it, the simulation runs again without any problems.
In the input.scs the lines 74-81 are:
// Library name: analogLib
// Cell name: ideal_balun
// View name: schematic
subckt ideal_balun d c p n
K0 (d 0 p c) transformer n1=2
K1 (d 0 c n) transformer n1=2
ends ideal_balun
// End of subcircuit definition.
And the lines 187-190:
// Library name: analogLib
// Cell name: ideal_balun
// View name: schematic
subckt ideal_balun d c p n
Could anyone explain what I'm doing wrong?
Thank you!
I have a testbench-schematic for an rectifier:
If I start Cadence and open this schematic and ADE GXL with the related adexl view and I run the simulation everything is alright. But if I subsequently "Check and Save" this schematic without any changes in the schematic and after that I klick "Run Simulation" again, then the simulation fails and in the output log I can read:
Warning from spectre in `ideal_balun', during circuit read-in.
WARNING (SFE-618): "input.scs" 190: Unterminated subcircuit. Terminating statement at the end of file.
.
.
.
Error found by spectre during circuit read-in.
ERROR (SFE-3): "input.scs" 190: `ideal_balun' is being redefined. It was defined at `input.scs' 77 before. Remove or rename either of them.
If I close ADE and reopen it, the simulation runs again without any problems.
In the input.scs the lines 74-81 are:
// Library name: analogLib
// Cell name: ideal_balun
// View name: schematic
subckt ideal_balun d c p n
K0 (d 0 p c) transformer n1=2
K1 (d 0 c n) transformer n1=2
ends ideal_balun
// End of subcircuit definition.
And the lines 187-190:
// Library name: analogLib
// Cell name: ideal_balun
// View name: schematic
subckt ideal_balun d c p n
Could anyone explain what I'm doing wrong?
Thank you!