I am not entirely sure on how the simulator works and why this do not show, this is the first thing I saw which was wrong with the design. I know that the ratio mentioned above will influence your threshold voltage, it is more of a analog design rule but it shows in the digital side. I cannot guarantee that this is the solution, it is a start.
The equivalent ratios for nMOS and pMOS networks should be the same.
I did the digital design course a while back. The following is a good book for future reference on digital CMOS design:
CMOS Digital Integrated Circuits Analysis & Design by Sung-Mo Kang & Yusuf Leblebici from McGraw-Hill with ISBN:978-0072460537