Cadence Systemverilog Testbenches: bind program blocks

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casey480

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All,

I am using the Cadence simulation toolset (ncelab, ncvlog) and trying to bind individual test programs to my testbench, but I am encountering problems at elaboration.

For example, i have

Code: 
module top_tb();

  my_device dut();

  my_test test();

endmodule

And I also have

Code: 
program test_a;

 //stuff

endprogram
and

Code: 
program test_b;

 //stuff

endprogram

I want to be able to elaborate and run either test_a or test_b in testbench top_tb at the test() instantiation.

Any insight?

Thanks.
 

Pass in a processor directive my_test to be either test_a or test_b from the command line.

So instead
my_test test();
becomes
`my_test test();
 

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    casey480

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RBB said:
Pass in a processor directive my_test to be either test_a or test_b from the command line.

So instead
my_test test();
becomes
`my_test test();
Click to expand...

Thanks, that works well.

But what if your test program has no ports, and drives everything via a commonly instanced module? Can you use configs & lib maps with the cadence tool set? It would be nice to have everything compiled into one library, and then run programs at will.

Added after 1 minutes:

ljxpjpjljx said:
Can anyone suggest goode SV methodology flow?
Click to expand...

Can you be more specific? Test methodology? RTL development? Here is a good SV verification book:

https://www.amazon.com/SystemVerilo...h-Language/dp/0387765298/ref=pd_bxgy_b_text_b
 

SV methodology , you should definitely go for OVM.

Cheers,
eChipDesign


=====================================================
eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil, TamilNadu

**broken link removed**

=====================================================
 

 

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