Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Cadence simulation NMOS and PMOS

Status
Not open for further replies.
L

lufer17

Member level 5
Joined
Jul 15, 2019
Messages
84
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
885
Hello everyone, I'm having difficulty simulating CADENCE, NMOS AND PMOS components are NOT enabled when making modifications, such as inserting values of width or length of their structures in the schematic [schematic]. It is impossible to do the simulation.

And in the layout there is no icon or individual cell phone NWELL or PWELL.
Does anyone have this manual or guide?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top