sankudey
Full Member level 3
Hi,
While simulating in Cadence Analog Design environment, I face the following problem. Any help would be of great value.
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Problem Description:The transistor count is approx. 5000 (7-bit ADC) for the circuit I want to simulate by spectre. I gave a "transient" simulation ("tran") from analog design environment for a period of ~ 525ns while the operating clock/signal is ~ 2.5GHz. The simulation is completed "successfilly" but the output shows that upto only 114.9ns the outputs are OK but there after all the voltage and current signals are straight line and bearing garbage value.
Please advice me for the same.
----------
Thanking in Anticipation
sankudey
While simulating in Cadence Analog Design environment, I face the following problem. Any help would be of great value.
------------
Problem Description:The transistor count is approx. 5000 (7-bit ADC) for the circuit I want to simulate by spectre. I gave a "transient" simulation ("tran") from analog design environment for a period of ~ 525ns while the operating clock/signal is ~ 2.5GHz. The simulation is completed "successfilly" but the output shows that upto only 114.9ns the outputs are OK but there after all the voltage and current signals are straight line and bearing garbage value.
Please advice me for the same.
----------
Thanking in Anticipation
sankudey