Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

cadence rtl compiler related

Status
Not open for further replies.

surajsasidarn

Newbie level 4
Joined
Mar 6, 2012
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,318
hi
how to synthesis a vhdl code which has hierarchy with cadence rtl compiler , can any one provide me with a sample tcl file
thanks in advance
 

hai friend,


you can refer this pdf to write a tcl script for doing synyhesis


thank you.
 

Attachments

  • Syn_Place_and_Rt_V2.pdf
    1.4 MB · Views: 83

The Below command works and gives the slack value of a timing path in ETS (Encounter Timing System). Can any one provide the equivalent command in RC?
get_attribute [report_timing -from paddr_ip[28] -to dl010lll02177/O1l0ll01164185l_reg[19]/D -collection] slack

Thanks,
Aravind
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top