Cadence RTL compiler error

[JineshKB]

sir am getting this message when I gave my TCL script.After this tool is not responding.My other designs are getting synthesised only problem with this sad_str.vhd.For this design am getting correct output in NCSIM (also the design was synthesisable in xilinx ISE)

Setting attribute of root '/': 'library' = tutorial.lib
Elaborating top-level block 'SAD_str' from file 'sad_str.vhd'.
Done elaborating 'SAD_str'.
Warning : This attribute will be obsolete in a next major release. [TUI-32]
: attribute: 'auto_ungroup_ok', object type: 'subdesign'
: Kindly use the new attribute 'ungroup_ok' which works across the flow.
Trying carrysave optimization (configuration 1 of 1) on module 'SAD_str_csa_cluster'...
Info : Done carrysave optimization. [RTLOPT-20]
: There are 2 CSA groups in module 'SAD_str_csa_cluster'... Accepted.
Mapping SAD_str to gates.

 

[sharath666]

It is a warning and not an error message. You can either ignore it or use the ungroup_ok command instead of the auto_ungroup_ok command.

 

[JineshKB]

It is a warning and not an error message. You can either ignore it or use the ungroup_ok command instead of the auto_ungroup_ok command.

Sir,but the tool is not responding after showing this message.its showing Mapping SAD_str to gates. after that nothing happens.

 

[sharath666]

I think you need to wait for some time. From the last message it looks like it is in the middle of optimization. This usually takes some time.