CADENCE RTL COMPILER clock gating

[dassubhajit02]

How can I do the clock gating in the RTL compiler in cadence. I have used the commands for clock gating and also implemented gating technique in my Verilog code but it is showing that the gated flip flops are zero. What should I do?

 

[ThisIsNotSam]

I suspect you have done something wrong by the way you describe it. What do you mean by "I implemented". There is no need to implement anything for CG, enables are automatically recognised.

If somehow you got it to work, just check your netlist.