Cadence RC compiler and Power Pins

[Deka87]

Good Moorning to all,

I am a newbie in the digital design tool. I have designed a clock divider in VHDL code and i've verified the behavioral using irun and an AMS simulation in Virtuoso. The next step was the conversion from RTL to gate level using RC Compiler.

I have used this simple script

#-----------------------------------------------------------------------------------------------------
#                                       Microelectronics Laboratory
#                               	   University of Bergamo
#                                   via Galvani 2 24044, Dalmine, Bergamo, Italy
#-----------------------------------------------------------------------------------------------------
# [File name]      synrtl.tcl

# [Technology]     TSMC 65nm CRN65LP/CLN65LP

# [Language]       Tcl/Cadence RTL Compiler commands
# [Created]        May 16, 2016
# [Modified]       May 16, 2016
# [Description]    script to synthesis RTL VHDL
# [Notes]          -
# [Version]        1.0
# [Revisions]      
#-----------------------------------------------------------------------------------------------------

set basename Clock_Divider;   # name of top level module
set runname prova          ;   # name appended to output files
set DESIGN Clock_Divider


###set MAP_EFF medium

set DATE [clock format [clock seconds] -format "%b%d-%T"] 
set _OUTPUTS_PATH outputs_${DATE}
set _REPORTS_PATH reports_${DATE}
set _LOG_PATH logs_${DATE}


##set ET_WORKDIR <ET work directory>
set_attribute lib_search_path {/opt/DK/TSMC65_VCAD_V1.7A_base/Base_PDK/digital/Front_End/timing_power_noise/ECSM/tcbn65lp_200a} / 
set_attribute hdl_search_path {/home/prin/RD53A_off_wd/IPS/sos/CLOCKDIVIDER} /




##set_attribute wireload_mode <value> /
set_attribute information_level 9 /

###############################################################
## Library setup
###############################################################
set_attribute library [path of the DK]/


####################################################################
## Load Design
####################################################################


read_hdl -vhdl CLOCKDIVIDER.vhd
elaborate $DESIGN
puts "Runtime & Memory after 'read_hdl'"
timestat Elaboration



check_design -unresolved

####################################################################
## Constraints Setup
####################################################################

#set clock [define_clock -period 25n -name myClk [clk#]]	

read_sdc "./sdc/clock.sdc"

report timing -lint

synthesize -to_generic

synthesize -to_mapped


# Write out the reports
report timing > ${basename}_${runname}_timing.rep
report gates  > ${basename}_${runname}_cell.rep
report power  > ${basename}_${runname}_power.rep

# Write out the structural Verilog and sdc files
write_hdl -mapped >  ${basename}_${runname}.v
write_sdc >  ${basename}_${runname}.sdc

and correctly the compiler converts to gate level.

But I have two problems during the simulation:


1) I've tried to import the verilog (synthesized) in virtuoso using the GUI verilogIN, but the schematic generated haven't the connections for VDD and VSS for each standard cells. (In the verilog synthetized for each instance there isn't any reference to VDD and VSS)

2) when i try to simulate the functional view, in the config view each standard cell haven't any reference to the standard cell to the DK. all lines are red.

There is anyone can help me?


Best Regard
Francesco

 

[ThisIsNotSam]

you need the verilog model of each standard cell. your standard cell provider should give that yo you. these models usually have a switch that creates the ports for VDD/GND.