Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence question concerning virtuoso design environment

Status
Not open for further replies.

saruman1983

Member level 2
Joined
Oct 12, 2005
Messages
46
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,288
Location
Greece
Activity points
1,563
Another cadence question

Hi all,

How can I simulate the transconductance of a transistor and generally a circuit vs. frequency in the cadence virtuoso design environment?
 

Re: Another cadence question

Hi

I am not sure if this is what you are after. If I am not mistaken, transconductance of a MOS transistor can be simulated in Cadence by doing a simple Ids/Vgs simulation. Then you open up the calculator and use the "deriv" function on the I/V curve. The output should be a transconductance curve for the transistor.
 

Another cadence question

I do simulation with above method, too.
 

Re: Another cadence question

OK, but what if i want to plot the (overall) transconductance of a MOS transistor (not gm, but Gm) for a common source connection for example? The above method requires a DC sweep, then taking the derivative of the curve to find transconductance. I was wondering if that can be done only with an AC analysis,that is when frequency varies and the parasitics of the transistor force the overall Gm to start decreasing.
 

Re: Another cadence question

plot square root of id VS Vgs(or vgs-vt) and find the slope...
then use the drain current equation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top